1. Field of the Invention
This invention relates to semiconductor devices and more particularly to Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) devices.
2. Description of Related Art
A typical polycide gate stack in a DRAM device includes a gate electrode stack, referred to below as a GC stack, that consists of the following composite sequence of layers: silicon/gate oxide/N+ doped polysilicon/WSi.sub.x /Cap-Insulator. The patterned N+ doped polysilicon and WSi.sub.x layers comprise the gate conductor (GC) in the gate electrode stack.
Fabrication of the polycide structure consists of an in situ doped polysilicon deposition, or polysilicon (or amorphous silicon) deposition followed by implantation of As+ or P+, followed in turn by wet cleaning and tungsten (WSi.sub.x) deposition either by sputtering or CVD (Chemical Vapor Deposition.) The problems encountered during the above process are as follows:
1) During post GC stack heat cycles, the dopant atoms in the polysilicon migrate into the WSi.sub.x layer. FIG. 21 shows a Secondary Ion Mass Spectrometry (SIMS) arsenic (As+) profile of the GC stack of 500 .ANG. N+ doped polysilicon/500 .ANG. WSi.sub.2.8 /2000 .ANG. Si.sub.3 N.sub.4. The profile shows dopant concentration versus depth from the surface of the GC stack. During the process, the dopant is distributed and piles up at the polysilicon/WSi.sub.x and WSi.sub.x /cap silicon nitride interfaces. Migration and pile up of dopants reduces the dopant concentration at the polysilicon/gate oxide interface resulting in a partially depleted gate that normally degrades the FET performance by increasing the equivalent oxide thickness t.sub.eq. PA1 2) High-dose implantation and thin film deposition steps frequently result in metal contamination of polysilicon and subsequent metal penetration into the gate oxide and silicon substrate, thereby degrading the oxide integrity and reliability and reducing the DRAM cell retention time. PA1 3) In dual workfunction CMOS (N+ polysilicon for NMOS and P+ polysilicon for PMOS), boron penetration through the PMOS gate degrades the gate oxide and MOSFET performance. Special precautions must be taken to avoid or minimize boron penetration, however, at the cost of increased process complexity and reduced flexibility. One example is the necessary avoidance of a nitride cap that is known to enhance penetration by generating excess hydrogen. PA1 Si/Gate Oxide/doped (N+ or P+) polysilicon/W.sub.y N/WSi.sub.x /Cap insulator. PA1 Si/Gate Oxide/N+ polysilicon/W.sub.y N/WSi.sub.x /Cap insulator.
U.S. Pat. No. 5,414,301 of M. E. Thomas for "High Temperature Interconnect System for an Integrated Circuit" describes use of Tungsten Nitride and Tungsten Silicide for barrier layers and interconnections in transistor structures; Col. 1, lines 5-15; Col. 2, lines 27-68; Col. 3, Lines 1-31; Col. 4, lines 34-68; Col. 5, lines 1-68; Col. 6, lines 1-28). As the title suggests, the Thomas patent is related to interconnects and not to a MOSFET gate stack. The main purpose of deposited barrier films is to inhibit the transport of silicon and subsequent creation of "spikes" in junctions, when the structure is subjected to temperatures in excess of 500.degree. C. The structure emphasizes titanium silicide and titanium nitride and focuses on electromigration and the Kirkendall effect in bipolar structures. In contrast, the present invention uses tungsten nitride as a barrier in conjunction with tungsten silicide in a polysilicon gate stack to inhibit the migration of metals and dopants toward and through the gate oxide which is a totally different approach and objective.
A publication entitled "Metal Diffusion Barrier Composite In Polycide Process" published in Research Disclosure, page 263 (March 1986) describes use of twin layers provided in a structure made by a polycide process. The first of the twin layers is a titanium nitride composite underlayer. The second of the twin layers is a thin metal layer composed of a metal selected from the group consisting of titanium, cobalt, and platinum. In the process disclosed, first a conducting, refractory metal nitride (TiN) layer is deposited on a polysilicon substrate. Next, the metal layer is deposited to complete the twin layers. Finally, a tungsten silicide layer is deposited over the composite twin metal layers (over the TiN layer). The twin layers act as a dopant diffusion barrier. However, in the publication the titanium nitride is used as the barrier metal and as an adhesion promoter. The path of dopant diffusion is not indicated. It appears that the method is aimed at inhibiting dopant diffusion from the source/drain regions.
U.S. Pat. No. 5,319,245 for "Local Interconnects for Integrated Circuits" of Chen et al. describes local interconnects for integrated circuits, where a refractory nitride is formed over the IC; and then a refractory metal silicide is deposited on the refractory nitride as a barrier layer (See Col. 1, lines 5-22; Col. 2, lines 1-16; Col. 3, lines 14-68; Col. 4, lines 1-46). The Chen et al. patent focuses on local interconnects. The method is illustrated for titanium, titanium nitride barrier, and tantalum silicide. The main objective is to form low-resistivity local interconnections (e.g., between source/drain and gate conductor) without causing "spikes" in the source/drain junctions. There is no mention of inhibiting metal or dopant diffusion into a gate oxide. The materials used are not suitable for this purpose due to their poor thermal stability.
U.S. Pat. No. 5,451,545, "Process for Forming Stable Local Interconnect/Active Area Silicide Structure VLSI Applications," of Ramaswami et al. describes a process in which titanium silicide is layered over a gate electrode; followed by a layer of titanium nitride; followed by a layer of titanium silicide; followed by a silicon (Si) layer (Col. 6-12, 45-68; Col. 2, lines 1-22; Col. 3, lines 1-68; Col. 4, lines 1-33). This patent also focuses on local interconnects. The materials used are titanium, titanium nitride, and titanium silicide. The main purpose is to form a barrier to oxygen, to improve adhesion and prevent peeling of the conducting film. The objectives, procedure, and materials used are completely different from those of the present invention.